18081C333MAT2A [KYOCERA AVX]
Ceramic Capacitor, Multilayer, Ceramic, 100V, 20% +Tol, 20% -Tol, X7R, 15% TC, 0.033uF, Surface Mount, 1808, CHIP;
| 型号： | 18081C333MAT2A |
| 厂家： | 
KYOCERA AVX |
| 描述： | Ceramic Capacitor, Multilayer, Ceramic, 100V, 20% +Tol, 20% -Tol, X7R, 15% TC, 0.033uF, Surface Mount, 1808, CHIP |
| 文件： | 总22页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X7R Dielectric
General Specifications
X7R formulations are called “temperature stable” ceramics
and fall into EIA Class II materials. X7R is the most popular
of these intermediate dielectric constant materials. Its tem-
perature variation of capacitance is within ±±15 from
-11°C to +±21°C. This capacitance change is non-linear.
Capacitance for X7R varies under the influence of electrical
operating conditions such as voltage and frequency.
X7R dielectric chip usage covers the broad spectrum of
industrial applications where known changes in capaci-
tance due to applied voltages are acceptable.
PART NUMBER (see page 3 for complete part number explanation)
0805
5
C
103
M
A
T
2
A
Size
(L" x W"z
Voltage
±0ꢀ = Z
±6ꢀ = Y
21ꢀ = 3
10ꢀ = 1
±00ꢀ = ±
Dielectric
X7R = C
Capacitance Capacitance
Failure
Rate
A = Not
Applicable
Terminations
T = Plated Ni
and Solder
Packaging
2 = 7" Reel
4 = ±3" Reel
Special
Code
A = Std.
Product
Code
Tolerance
Preferred
M = ± 205
K = ±±05
PERFORMANCE CHARACTERISTICS
Capacitance Range
±00 pF to 2.2 µF (±.0 ±0.2 ꢀrmsꢁ ±kꢂHz
Capacitance Tolerances
Preferred ±±05ꢁ ±205
others available: ±15ꢁ +ꢃ0 ꢄ205
Operating Temperature Range
Temperature Characteristic
Voltage Ratings
-11°C to +±21°C
±±15 (0 ꢀVCz
±0ꢁ ±6ꢁ 21ꢁ 10ꢁ ±00 ꢀVC (+±21°Cz
Dissipation Factor
For 10 volts and ±00 volts: 2.15 max.
For 21 volts: 3.05 max.
For ±6 volts: 3.15 max.
For ±0 volts: 15 max.
Insulation Resistance (+21°Cꢁ RꢀVCz
Insulation Resistance (+±21°Cꢁ RꢀVCz
Dielectric Strength
±00ꢁ000 megohms min. or ±000 MΩ - µF min.ꢁ whichever is less
±0ꢁ000 megohms min. or ±00 MΩ - µF min.ꢁ whichever is less
2105 of rated voltage for 1 seconds at 10 mamp max. current
±.0 ± 0.2 ꢀrms
Test Voltage
Test Frequency
± KꢂH
8
X7R Dielectric
Typical Characteristic Curves**
Variation of Impedance with Cap Value
Impedance vs. Frequency
1,000 pF vs. 10,000 pF - X7R
0805
Temperature Coefficient
+12
+6
0
10.00
1,000 pF
10,000 pF
-6
1.00
-12
-18
-24
0.10
0.01
-75 -50
+125
+25 +50 +75 +100
-25
0
Temperature °C
100
1000
10
Frequency, MHz
Variation of Impedance with Chip Size
Impedance vs. Frequency
10,000 pF - X7R
⌬ Capacitance vs. Frequency
10
1206
0805
1210
+20
+10
1.0
0
-10
-20
0.1
.01
100
1,000
1
10
1KHz
10 KHz
100 KHz
1 MHz
10 MHz
Frequency, MHz
Frequency
Variation of Impedance with Chip Size
Impedance vs. Frequency
100,000 pF - X7R
Insulation Resistance vs Temperature
10,000
1,000
100
10
1206
0805
1210
1.0
0.1
.01
0
+20
+40
+60
+80 +100
+25
100
1,000
1
10
Temperature °C
Frequency, MHz
SUMMARY OF CAPACITANCE RANGES VS. CHIP SIZE
Style
0402*
0504
10V
16V
25V
50V
100V
—
±00pF - 47nF
±00pF - 6.ꢃnF
±00pF - 3.9nF
±00pF - .0±µF
±00pF - ±1nF
±00pF - 0.±µF
±nF - 0.22µF
±nF - 0.22µF
±nF - 0.±µF
±0nF - 0.33µF
±0nF - ±µF
—
—
—
—
±00pF - 3.3nF
±00pF - 4.7nF
±00pF - 22nF
±nF - 0.±µF
±nF - 0.±µF
±nF - 27nF
0603*
0805*
1206*
1210*
1505
±00pF - 0.22µF
±00pF - 0.±µF
±00pF - 47nF
±00pF - 2.2µF
±00pF - 0.47µF
±00pF - 0.22µF
±.1µF - 4.7µF
±nF - ±µF
±nF - ±.0µF
→
→
→
→
→
→
→
±nF - ±.ꢃµF
±nF - ±µF
→
→
→
→
→
→
→
1808
±0nF - 0.33µF
±0nF - 0.±µF
±0nF - 0.47µF
±0nF - 0.47µF
±0nF - ±.2µF
±0nF - ±.1µF
1812*
1825*
2220
→
→
→
→
±0nF - ±µF
±0nF - ±.1µF
±0nF - 2.2µF
2225
* Standard SiHes
** For additional information on performance changes with operating conditions consult AꢀX’s software SpiCap.
9
X7R Dielectric
Capacitance Range
PREFERRED SIZES ARE SHADED
SIZE
0402*
0504*
0603*
0805
1206
1505
Standard Reel
Packaging
All Paper
All Embossed
All Paper
Paper/Embossed
Paper/Embossed
All Embossed
MM
(in.z
±.00 ± .±0
(.040 ± .004z
±.27 ± .21
(.010 ± .0±0z
±.60 ± .±1
(.063 ± .006z
2.0± ± .20
(.079 ± .00ꢃz
3.20 ± .20
(.±26 ± .00ꢃz
3.ꢃ± ± .21
(.±10 ± .0±0z
(Lz Length
MM
(in.z
.10 ± .±0
(.020 ± .004z
±.02 ± .21
(.040 ± .0±0z
.ꢃ± ± .±1
(.032 ± .006z
±.21 ± .20
(.049 ± .00ꢃz
±.60 ± .20
(.063 ± .00ꢃz
±.27 ± .21
(.010 ± .0±0z
(Wz Width
MM
(in.z
.60
(.024z
±.02
(.040z
.90
(.031z
±.30
(.01±z
±.10
(.019z
±.27
(.010z
(Tz Max. Thickness
MM
(in.z
.21 ± .±1
.3ꢃ ± .±3
.31 ± .±1
.10 ± .21
.10 ± .21
.10 ± .21
(tz Terminal
WꢀVC
(.0±0 ± .006z
(.0±1 ± .001z
(.0±4 ± .006z
(.020 ± .0±0z
(.020 ± .0±0z
(.020 ± .0±0z
±6
21
10
10
±00
±0
±6
21
10 ±00 ±0
±6
21
10 ±00
±0
±6
21
10 ±00
10
±00
Cap
(pFz
±00
±20
±10
W
L
᭢
T
±ꢃ0
220
270
᭢
330
390
470
t
160
6ꢃ0
ꢃ20
±000
±200
±100
±ꢃ00
2200
2700
3300
3900
4700
1600
6ꢃ00
ꢃ200
Cap.
(µFz
.0±0
.0±2
.0±1
.0±ꢃ
.022
.027
.033
.039
.047
.016
.06ꢃ
.0ꢃ2
.±0
.±2
.±1
.±ꢃ
.22
.27
.33
.47
.16
.6ꢃ
.ꢃ2
±.0
±.2
±.1
±.ꢃ
2.2
4.7
= Paper Tape
= Embossed Tape
*Reflow soldering only.
NOTES: For higher voltage chips, see pages 20 and 21.
10
X7R Dielectric
Capacitance Range
PREFERRED SIZES ARE SHADED
SIZE
1210
1808*
1812*
1825*
2220*
2225*
Standard Reel Packaging
Paper/Embossed
All Embossed
All Embossed
All Embossed
All Embossed
All Embossed
MM
(in.z
3.20 ± .20
(.±26 ± .00ꢃz
4.17 ± .21
(.±ꢃ0 ± .0±0z
4.10 ± .30
(.±77 ± .0±2z
4.10 ± .30
(.±77 ± .0±2z
1.7 ± 0.4
(.221 ± .0±6z
1.72 ± .21
(.221 ± .0±0z
(L) Length
MM
(in.z
2.10 ± .20
(.09ꢃ ± .00ꢃz
2.03 ± .21
(.0ꢃ0 ± .0±0z
3.20 ± .20
(.±26 ± .00ꢃz
6.40 ± .40
(.212 ± .0±6z
1.0 ± 0.4
(.±97 ± .0±6z
6.31 ± .21
(.210 ± .0±0z
(Wz Width
MM
(in.z
MM
(in.z
±.70
±.12
±.70
±.70
2.30
±.70
(Tz Max. Thickness
(tz Terminal
(.067z
(.060z
(.067z
(.067z
(.090z
(.067z
.10 ± .21
(.020 ± .0±0z
.64 ± .39
(.021 ± .0±1z
.6± ± .36
(.024 ± .0±4z
.6± ± .36
(.024 ± .0±4z
.64 ± .39
(.021 ± .0±1z
.64 ± .39
(.021 ± .0±1z
WꢀVC
±6
21
10
±00
21
10
±00
10
±00
10
±00
10
±00
200
10
±00
Cap
(pFz
±000
±200
±100
W
L
᭢
±ꢃ00
2200
2700
T
᭢
3300
3900
4700
t
1600
6ꢃ00
ꢃ200
Cap.
(µFz
.0±0
.0±2
.0±1
.0±ꢃ
.022
.027
.033
.039
.047
.016
.06ꢃ
.0ꢃ2
.±0
.±2
.±1
.±ꢃ
.22
.27
.33
.39
.47
.16
.6ꢃ
.ꢃ2
±.0
±.2
±.1
±.ꢃ
2.2
*Reflow soldering only.
= Paper Tape
= Embossed Tape
NOTES: For higher voltage chips, see pages 20 and 21.
11
Basic Capacitor Formulas
I. Capacitance (farads)
XI. Equivalent Series Resistance (ohms)
.224 K A
E.S.R. = (V.F.z (Xcz = (V.F.z / (2 π fCz
English: C =
TV
XII. Power Loss (watts)
.0ꢃꢃ4 K A
2
Metric: C =
Power Loss = (2 π fCꢀ z (V.F.z
TV
XIII. KVA (Kilowatts)
II. Energy stored in capacitors (Joules, watt - sec)
-3
2
KꢀA = 2 π fCꢀ x ±0
2
±
E = ⁄
2
Cꢀ
XIV. Temperature Characteristic (ppm/°C)
III. Linear charge of a capacitor (Amperes)
6
Ct ꢄ C21
C21 (Tt ꢄ 21z
dꢀ
dt
T.C. =
x ±0
I = C
XV. Cap Drift (%)
IV. Total Impedance of a capacitor (ohms)
C± ꢄ C2
C±
2
2
ͱ
C.V. =
x ±00
Z = RS + (X - X z
C
L
V. Capacitive Reactance (ohms)
XVI. Reliability of Ceramic Capacitors
±
x =
c
L0
Lt
ꢀt
ꢀo
X
Tt
To
Y
=
2 π fC
( z ( z
VI. Inductive Reactance (ohms)
XVII. Capacitors in Series (current the same)
xL = 2 π fL
Any Number:
±
C
±
±
C2
±
---
=
+
VII. Phase Angles:
C±
C
N
T
Ideal Capacitors: Current leads voltage 90°
Ideal Inductors: Current lags voltage 90°
Ideal Resistors: Current in phase with voltage
C± C2
C± + C2
Two: C =
T
XVIII. Capacitors in Parallel (voltage the same)
VIII. Dissipation Factor (%)
C = C± + C2 --- + C
T
N
E.S.R.
V.F.= tan ␦ (loss anglez =
= (2 πfCz (E.S.R.z
X
XIX. Aging Rate
c
IX. Power Factor (%)
A.R. = 5D C/decade of time
P.F. = Sine ␦ (loss anglez = Cos (phase anglez
P.F. = (when less than ±05z = VF
f
XX. Decibels
db = 20 log
ꢀ±
ꢀ2
X. Quality Factor (dimensionless)
±
V.F.
Q = Cotan ␦ (loss anglez =
METRIC PREFIXES SYMBOLS
-±2
K
A
TV
ꢀ
t
= Vielectric Constant
= Area
f
= frequency
= Inductance
= Loss angle
= Phase angle
Lt
= Test life
Pico
Nano
Micro
Milli
Veci
Veca
Kilo
Mega
Giga
Tera
X ±0
X ±0
X ±0
X ±0
X ±0
X ±0
X ±0
X ±0
X ±0
X ±0
-9
L
␦
ꢀt
ꢀo
Tt
= Test voltage
-6
-3
= Vielectric thickness
= ꢀoltage
= Operating voltage
= Test temperature
= Operating temperature
-±
+±
+3
+6
+9
+±2
f
= time
X & Y = exponent effect of voltage and temp.
To
R
= Series Resistance
Lo
= Operating life
s
2
How to Order
Part Number Explanation
EXAMPLE: 08055A101JAT2A
0805
5
A
101
J
A
T
2
A
SiHe
(L" x W"z
0402
0104
0603
0805
±001
0907
1206
1210
±101
±ꢃ01
±ꢃ0ꢃ
1812
1825
2221
3640
Dielectric
C0G (NP0z = A
X7R = C
Capacitance
Tolerance
C = ±.21 pF*
V = ±.10 pF*
F = ±±5 (≥ 21 pFz
G = ±25 (≥ ±3 pFz
J = ±15
K = ±±05
M = ±205
Z = +ꢃ05ꢁ -205
P = +±005ꢁ -05
Terminations
Special**
Code
Standard:
T = Ni and Tin
Plated
A = Standard
Product
X1R = V
Z1U = E
Y1ꢀ = G
Non-Standard
P = Embossed
unmarked
M = Embossed
marked
E = Standard
packaging
Others:
7 = Plated Ni
Gold Plated
± = Pd/Ag
marked
Low Profile
Chips Only
Max. Thickness
T = .66mm (.026"z
S = .16mm (.022"z
R = .46mm (.0±ꢃ"z
Voltage
±0ꢀ = Z
Capacitance
Code
Failure
Rate
A = Not
Applicable
±6ꢀ = Y
(2 significant
digits + no. of
Herosz
21ꢀ = 3
10ꢀ = 1
±00ꢀ = ±
200ꢀ = 2
210ꢀ = ꢀ
100ꢀ = 7
600ꢀ = C
±000ꢀ = A
±100ꢀ = S
2000ꢀ = G
2100ꢀ = W
3000ꢀ = ꢂ
4000ꢀ = J
1000ꢀ = K
Examples:
Packaging**
±0 pF = ±00
±00 pF = ±0±
±ꢁ000 pF = ±02
Recommended:
2 =7" Reel
4 =±3" Reel
22ꢁ000 pF = 223
220ꢁ000 pF = 224
± µF = ±01
Others:
7 = Bulk Cassette
9 = Bulk
For values below ±0 pFꢁ
use “R” in place of
decimal pointꢁ e.g.ꢁ 9.±
pfd = 9R±.
*C&V tolerances for Յ±0 pF values.
** Standard Tape and Reel material depends upon chip siHe and thickness.
See individual part tables for tape material type for each capacitance value.
Note: Unmarked product is standard. Marked product is available on special requestꢁ please contact AꢀX.
Standard packaging is shown in the individual tables.
Non-standard packaging is available on special requestꢁ please contact AꢀX.
3
General Specifications
Environmental
MOISTURE RESISTANCE
Specification
THERMAL SHOCK
Specification
Appearance
No visual defects
Appearance
No visual defects
Capacitance Variation
C0G (NP0z: ± 2.15 or ± .21pFꢁ whichever is greater
X7R: ≤ ± 7.15
Capacitance Variation
C0G (NP0z: ± 15 or ± .1pFꢁ whichever is greater
X7R: ≤ ± ±05
Z1U: ≤ ± 205
Z1U: ≤ ± 305
Y1ꢀ: ≤ ± 205
Y1ꢀ: ≤ ± 305
Q, Tan Delta
Q, Tan Delta
To meet initial requirement
C0G (NP0z:≥ 30pF........................Q ≥ 310
≥ ±0pFꢁ < 30pF...........Q ≥ 271+1C/2
< ±0pF ........................Q ≥ 200+±0C
X7R: Initial requirement + .15
Z1U: Initial requirement + ±5
Y1ꢀ: Initial requirement + 25
Insulation Resistance
C0G (NP0zꢁ X7R: To meet initial requirement
Z1Uꢁ Y1ꢀ: ≥ Initial ꢀalue x 0.±
Dielectric Strength
No problem observed
Insulation Resistance
≥ Initial ꢀalue x 0.3
Measuring Conditions
Step
Temperature °C
Time (minutes)
Measuring Conditions
C0G (NP0zꢁ X7R: -11° ± 2°
Z1U: +±0° ± 2°
±
30 ± 3
Step
Temp. °C
Humidity % Time (hrs)
Y1ꢀ: -30° ± 2°
±
+21->+61
+61
+61->+21
+21->+61
+61
+61->+21
+21
90-9ꢃ
90-9ꢃ
2.1
3.0
2.1
2.1
3.0
2.1
2.0
ꢄ
2
3
Room Temperature
C0G (NP0zꢁ X7R: +±21° ± 2°
Z1Uꢁ Y1ꢀ: +ꢃ1° ± 2°
# 3
2
3
ꢃ0-9ꢃ
30 ± 3
4
90-9ꢃ
4
Room Temperature
# 3
1
90-9ꢃ
6
ꢃ0-9ꢃ
Repeat for 1 cycles and measure after 4ꢃ hours ± 4 hours
(24 hours for C0G (NP0zz at room temperature.
7
90-9ꢃ
7a
7b
-±0
+21
uncontrolled
90-9ꢃ
ꢄ
IMMERSION
Specification
Repeat 20 cycles (±-7z and store for 4ꢃ hours (24 hours
for C0G (NP0zz at room temperature before measuring.
Steps 7a & 7b are done on any 1 out of first 9 cycles.
Appearance
No visual defects
Capacitance Variation
C0G (NP0z: ± 2.15 or ± .21pFꢁ whichever is greater
X7R: ≤ ± 7.15
Z1U: ≤ ± 205
Y1ꢀ: ≤ ± 205
Q, Tan Delta
To meet initial requirement
Insulation Resistance
C0G (NP0zꢁ X7R: To meet initial requirement
Z1Uꢁ Y1ꢀ: ≥ Initial ꢀalue x 0.±
Dielectric Strength
No problem observed
Measuring Conditions
Step
Temperature °C
Time (minutes)
+61 +1/-0
Pure Water
±
±1 ± 2
0 ± 3
NaCl solution
2
±1 ± 2
Repeat cycle 2 times and wash with water and dry.
Store at room temperature for 4ꢃ ± 4 hours (24 hours for
C0G (NP0zz and measure.
22
General Specifications
Environmental
STEADY STATE HUMIDITY
(No Load)
Insulation Resistance
C0G (NP0zꢁ X7R: To meet initial value x 0.3
Z1Uꢁ Y1ꢀ: ≥ Initial ꢀalue x 0.±
Specification
Charge devices with rated voltage in test chamber set
at ꢃ1 ± 15 relative humidity and ꢃ1°C for ±000
(+4ꢃꢁ-0z hours. Remove from test chamber and
stabiliHe at room temperature and humidity for 4ꢃ ± 4
hours (24 ±2 hours for C0G (NP0zz before measuring.
Appearance
No visual defects
Capacitance Variation
C0G (NP0z: ± 15 or ± .1pFꢁ whichever is greater
X7R: ≤ ± ±05
Charge and discharge currents must be less than
10ma.
Z1U: ≤ ± 305
Y1ꢀ: ≤ ± 305
Q, Tan Delta
C0G (NP0z: ≥ 30pF......................Q ≥ 310
≥ ±0pFꢁ < 30pF.........Q ≥ 271+1C/2
< ±0pF ....................Q ≥ 200+±0C
X7R: Initial requirement + .15
Z1U: Initial requirement + ±5
Y1ꢀ: Initial requirement + 25
LOAD LIFE
Specification
Appearance
No visual defects
Insulation Resistance
≥ Initial ꢀalue x 0.3
Capacitance Variation
C0G (NP0z: ± 35 or ± .3pFꢁ whichever is greater
X7R: ≤ ± ±05
Measuring Conditions
Z1U: ≤ ± 305
Y1ꢀ: ≤ ± 305
Store at ꢃ1 ± 15 relative humidity and ꢃ1°C for ±000
hoursꢁ without voltage. Remove from test chamber
and stabiliHe at room temperature and humidity for
4ꢃ ± 4 hours (24 ±2 hours for C0G (NP0zz before
measuring.
Q, Tan Delta
C0G (NP0z: ≥ 30pF......................Q ≥ 310
≥ ±0pFꢁ < 30pF.........Q ≥ 271+1C/2
< ±0pF ....................Q ≥ 200+±0C
X7R: Initial requirement + .15
Z1U: Initial requirement + ±5
Y1ꢀ: Initial requirement + 25
Charge and discharge currents must be less than
10ma.
Insulation Resistance
C0G (NP0zꢁ X7R: To meet initial value x 0.3
Z1Uꢁ Y1ꢀ: ≥ Initial ꢀalue x 0.±
LOAD HUMIDITY
Specification
Charge devices with twice rated voltage in test
chamber set at +±21°C ± 2°C for C0G (NP0z and X7Rꢁ
+ꢃ1° ± 2°C for Z1Uꢁ and Y1ꢀ for ±000 (+4ꢃꢁ-0z hours.
Remove from test chamber and stabiliHe at room
temperature for 4ꢃ ± 4 hours (24 ±2 hours for C0G
(NP0zz before measuring.
Appearance
No visual defects
Capacitance Variation
C0G (NP0z: ± 15 or ± .1pFꢁ whichever is greater
X7R: ≤ ± ±05
Z1U: ≤ ± 305
Y1ꢀ: ≤ ± 305
Charge and discharge currents must be less than
10ma.
Q, Tan Delta
C0G (NP0z: ≥ 30pF .....................Q ≥ 310
≥ ±0pFꢁ< 30pF.........Q ≥ 271+1C/2
< ±0pF ....................Q ≥ 200+±0C
X7R: Initial requirement + .15
Z1U: Initial requirement + ±5
Y1ꢀ: Initial requirement + 25
23
General Specifications
Mechanical
END TERMINATION ADHERENCE
BEND STRENGTH
Specification
Speed = 1mm/sec
No evidence of peeling of end terminal
2mm
Deflection
Measuring Conditions
R340mm
After soldering devices to circuit board apply 1N
(0.1±kg fz for ±0 ± ± secondsꢁ please refer to Figure ±.
Supports
45mm
45mm
5N FORCE
Figure 2. Bend Strength
Specification
Appearance:
DEVICE UNDER TEST
Figure 1.
Terminal Adhesion
No visual defects
TEST BOARD
Capacitance Variation
C0G (NP0z: ± 15 or ± .1pFꢁ whichever is larger
X7R: ≤ ± ±25
RESISTANCE TO VIBRATION
Specification
Z1U: ≤ ± 305
Y1ꢀ: ≤ ± 305
Appearance:
No visual defects
Insulation Resistance
C0G (NP0z: ≥ Initial ꢀalue x 0.3
X7R: ≥ Initial ꢀalue x 0.3
Z1U: ≥ Initial ꢀalue x 0.±
Y1ꢀ: ≥ Initial ꢀalue x 0.±
Capacitance
Within specified tolerance
Q, Tan Delta
To meet initial requirement
Measuring Conditions
Please refer to Figure 2
Insulation Resistance
C0G (NP0zꢁ X7R Ն Initial ꢀalue x 0.3
Z1Uꢁ Y1ꢀ Ն Initial ꢀalue x 0.±
Deflection:
2mm
Measuring Conditions
Test Time:
30 seconds
Vibration Frequency
±0-2000 ꢂH
RESISTANCE TO SOLDER HEAT
Maximum Acceleration
20G
Specification
Swing Width
Appearance:
No serious defectsꢁ <215 leaching of either end
terminal
±.1mm
Test Time
Xꢁ Yꢁ Z axis for 2 hours eachꢁ total 6 hours of test
Capacitance Variation
C0G (NP0z: ± 2.15 or ± 2.1pFꢁ whichever is greater
X7R: ≤ ± 7.15
SOLDERABILITY
Specification
Z1U: ≤ ± 205
Y1ꢀ: ≤ ± 205
Ն 915 of each termination end should be covered with
fresh solder
Q, Tan Delta
To meet initial requirement
Measuring Conditions
Insulation Resistance
Vip device in eutectic solder at 230 ± 1°C for
2 ± .1 seconds
To meet initial requirement
Dielectric Strength
No problem observed
Measuring Conditions
Vip device in eutectic solder at 260°Cꢁ for ± minute.
Store at room temperature for 4ꢃ hours (24 hours for
C0G (NP0zz before measuring electrical parameters.
Part siHes larger than 3.20mm x 2.49mm are reheated
at ±10°C for 30 ±1 seconds before performing test.
24
European Detail Specifications
CECC 32 101-801/Chips
Standard European Ceramic Chip Capacitors
PART NUMBER (example)
0805
5
C
103
M
T
T
2
A
Size
(L" x W"z
Voltage
10ꢀ = 1
±00ꢀ = ±
200ꢀ = 2
Dielectric
±B CG = A
2R± = C
Capacitance Capacitance Specification Terminations
Marking
Packaging
2 = 7" Reel
4 = ±3" Reel
Special
Code
A = Std.
Product
Code
Tolerance
See Vielectrics
C0Gꢁ X7Rꢁ Y1ꢀ
CECC32±0±-ꢃ0± T = Plated Ni
and Sn
2F4 = G
RANGE OF APPROVED COMPONENTS
Voltage and Capacitance Range
100V
Case
Size
Dielectric
Type
50V
200V
1BCG
0603
0ꢃ01
±206
±2±0
±ꢃ0ꢃ
±ꢃ±2
2220
±B CG
±B CG
±B CG
±B CG
±B CG
±B CG
±B CG
0.47pF - ±10pF
0.47pF - 160pF
0.47pF - 3.3nF
0.47pF - 4.7nF
0.47pF - 6.ꢃnF
0.47pF - ±1nF
0.47pF - 39nF
0.47pF - ±20pF
0.47pF - 160pF
0.47pF - 3.3nF
0.47pF - 4.7nF
0.47pF - 6.ꢃnF
0.47pF - ±1nF
0.47pF - 39nF
0.47pF - ±00pF
0.47pF - 330pF
0.47pF - ±.1nF
0.47pF - 2.7nF
0.47pF - 4.7nF
0.47pF - ±0nF
0.47pF - ±1nF
2R1
2F4
0603
0ꢃ01
±206
±2±0
±ꢃ0ꢃ
±ꢃ±2
2220
2R±
2R±
2R±
2R±
2R±
2R±
2R±
±0pF - 6.ꢃnF
±0pF - 33nF
±0pF - ±00nF
±0pF - ±10nF
±0pF - 270nF
±0pF - 470nF
±0pF - ±.2µF
±0pF - 6.ꢃnF
±0pF - ±ꢃnF
±0pF - 6ꢃnF
±0pF - ±00nF
±0pF - ±ꢃ0nF
±0pF - 330nF
±0pF - 6ꢃ0nF
±0pF - ±.2nF
±0pF - 3.3nF
±0pF - ±ꢃnF
±0pF - 27nF
±0pF - 47nF
±0pF - ±00nF
±0pF - 220nF
0ꢃ01
±206
±2±0
±ꢃ0ꢃ
±ꢃ±2
2220
2F4
2F4
2F4
2F4
2F4
2F4
±0pF - ±00nF
±0pF - 330nF
±0pF - 470nF
±0pF - 160nF
±0pF - ±.ꢃµF
±0pF - 2.2µF
31
Packaging of Chip Components
Automatic Insertion Packaging
TAPE & REEL QUANTITIES
All tape and reel specifications are in compliance with RS4ꢃ±.
ꢃmm
±2mm
Paper or Embossed Carrier
Embossed Only
0ꢃ01ꢁ ±001ꢁ ±206ꢁ
±2±0
0104ꢁ 0907
±101ꢁ ±ꢃ01ꢁ
±ꢃ0ꢃ
±ꢃ±2ꢁ ±ꢃ21
2220ꢁ 2221
Paper Only
0402ꢁ 0603
2ꢁ000 or 4ꢁ000(±z
±0ꢁ000
Qty. per Reel/7" Reel
3ꢁ000
±ꢁ000
4ꢁ000
Qty. per Reel/±3" Reel
±0ꢁ000
(±z Vependent on chip thickness. Low profile chips shown on page 27 are 1ꢁ000 per reel for 7" reel. 0402 siHe chips are ±0ꢁ000 per 7" reels and are
not available on ±3" reels. For 3640 siHe chip contact factory for quantity per reel.
REEL DIMENSIONS
Tape
A
Max.
B*
Min.
D*
Min.
N
Min.
W2
Max.
C
W1
W3
Size(1)
7.9 Min.
(.3±±z
ꢃ.4+ꢄ±0..00
±4.4
ꢃmm
+.060
(.33±
z
(.167z
±0.9 Max.
(.429z
ꢄ0.0
330
(±2.992z
±.1
(.019z
±3.0±0.20
(.1±2±.00ꢃz
20.2
(.791z
10
(±.969z
±±.9 Min.
(.469z
±1.4 Max.
(.607z
±2.4+ꢄ20..00
±ꢃ.4
(.724z
±2mm
+.076
(.4ꢃꢃ
z
ꢄ0.0
Metric dimensions will govern.
English measurements rounded and for reference only.
(1) For tape sizes 16mm and 24mm (used with chip size 3640) consult EIA RS-481 latest revision.
32
Embossed Carrier Configuration
8 & 12mm Tape Only
8 & 12mm Embossed Tape
Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size
D0
E
P0
P2
T Max.
T1
G1
G2
ꢃmm
and
±2mm
ꢃ.4+-00..0±0
±.71 ± 0.±0
4.0 ± 0.±0
2.0 ± 0.01
0.600
(.024z
0.±0
(.004z
Max.
0.71
0.71
+.004
(.019
-0.0
z
(.069 ± .004z (.±17 ± .004z (.079 ± .002z
(.030z
(.030z
Min.
Min.
See Note 3
See Note 4
VARIABLE DIMENSIONS
Tape Size
B1
D1
F
P1
R
T2
W
A0 B0 K0
Max.
Min.
Min.
See Note 6 See Note 5
See Note 2
ꢃ.0+-00..±3
4.11
±.0
3.1 ± 0.01
4.0 ± 0.±0
21
2.1 Max
(.09ꢃz
ꢃmm
See Note ±
See Note ±
See Note ±
See Note ±
(.3±1+-..000±42
z
(.±79z
(.039z
(.±3ꢃ ± .002z (.±17 ± .004z
(.9ꢃ4z
ꢃ.2
(.323z
±.1
(.019z
1.1 ± 0.01
(.2±7 ± .002z (.±17 ± .004z
4.0 ± 0.±0
30
(±.±ꢃ±z
6.1 Max.
(.216z
±2.0 ± .30
(.472 ± .0±2z
±2mm
ꢃ.0+-00..±3
ꢃmm
±/2 Pitch
4.11
(.±79z
±.0
(.039z
3.1 ± 0.01
(.±3ꢃ ± .002z 0.79 ± .004
2.0 ± 0.±0
21
(.9ꢃ4z
2.1 Max.
(.09ꢃz
(.3±1+-..000±42
z
±2mm
Vouble
Pitch
ꢃ.2
(.323z
±.1
(.019z
1.1 ± 0.01
(.2±7 ± .002z (.3±1 ± .004z
ꢃ.0 ± 0.±0
30
(±.±ꢃ±z
6.1 Max.
(.216z
±2.0 ± .30
(.472 ± .0±2z
NOTES:
±. A0ꢁ B0ꢁ and K0 are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body dimensions of the component. The
clearance between the end of the terminals or body of the component to the sides and depth of the cavity (A0ꢁ B0ꢁ and K0z must be within 0.01 mm (.002z min. and 0.10 mm
(.020z max. The clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (see sketches C & Vz.
2. Tape with components shall pass around radius “R” without damage. The minimum trailer length (Note 2 Fig. 3z may require additional length to provide R min. for ±2 mm
embossed tape for reels with hub diameters approaching N min. (Table 4z.
3. G± dimension is the flat area from the edge of the sprocket hole to either the outward deformation of the carrier tape between the embossed cavities or to the edge of the
cavity whichever is less.
4. G2 dimension is the flat area from the edge of the carrier tape opposite the sprocket holes to either the outward deformation of the carrier tape between the embossed cavity
or to the edge of the cavity whichever is less.
1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment.
Vimensions of embossment location and hole location shall be applied independent of each other.
6. B± dimension is a reference dimension for tape feeder clearance only.
33
Paper Carrier Configuration
8 & 12mm Tape Only
8 & 12mm Paper Tape
Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size
D0
E
P0
P2
T1
G1
G2
R MIN.
+0.±
ꢃmm
and
±2mm
±.1 -0.0
±.71 ± 0.±0
4.0 ± 0.±0
2.0 ± 0.01
0.±0
(.004z
Max.
0.71
(.030z
Min.
0.71
(.030z
Min.
21 (.9ꢃ4z
See Note 2
+.004
-.000
(.019
z
(.069 ± .004z (.±17 ± .004z (.079 ± .002z
VARIABLE DIMENSIONS
Tape Size
P1
F
W
A0 B0
See Note ±
T
ꢃ.0+-00..±3
ꢃmm
4.0 ± 0.±0
(.±17 ± .004z
3.1 ± 0.01
(.±3ꢃ ± .002z
See Note 3
(.3±1+-..000±42
z
4.0 ± .0±0
(.±17 ± .004z
1.1 ± 0.01
(.2±7 ± .002z
±2.0 ± 0.3
(.472 ± .0±2z
±2mm
ꢃ.0+-00..±3
ꢃmm
±/2 Pitch
2.0 ± 0.±0
(.079 ± .004z
3.1 ± 0.01
(.±3ꢃ ± .002z
(.3±1+-..000±42
z
±2mm
Vouble
Pitch
ꢃ.0 ± 0.±0
(.3±1 ± .004z
1.1 ± 0.01
(.2±7 ± .002z
±2.0 ± 0.3
(.472 ± .0±2z
NOTES:
±. A0ꢁ B0ꢁ and T are determined by the max. dimensions to the ends of the terminals extending from the component body and/or the body dimensions of the component. The
clearance between the ends of the terminals or body of the component to the sides and depth of the cavity (A0ꢁ B0ꢁ and Tz must be within 0.01 mm (.002z min. and 0.10 mm
(.020z max. The clearance allowed must also prevent rotation of the component within the cavity of not more than 20 degrees (see sketches A & Bz.
2. Tape with components shall pass around radius “R” without damage.
3. ±.± mm (.043z Base Tape and ±.6 mm (.063z Max. for Non-Paper Base Compositions.
Bar Code Labeling Standard
AꢀX bar code labeling is available and follows latest version of EIA-116-A.
34
Bulk Case Packaging
BENEFITS
BULK FEEDER
• Easier handling
• Smaller packaging volume
(1/20 of T/R packaging)
• Easier inventory control
• Flexibility
Case
Cassette
• Recyclable
Gate
Shooter
CASE DIMENSIONS
Shutter
Slider
12mm
36mm
Mounter
Head
Expanded Drawing
110mm
Chips
Attachment Base
CASE QUANTITIES
Part Size
0402
0603
0805
Qty.
(pcs / cassette)
10,000 (T=0.6mm)
5,000 (T¯≥0.6mm)
80,000
15,000
35
General Description
Basic Construction – A multilayer ceramic (MLCz capaci-
tor is a monolithic block of ceramic containing two sets of
offsetꢁ interleaved planar electrodes that extend to two
opposite surfaces of the ceramic dielectric. This simple
structure requires a considerable amount of sophisticationꢁ
both in material and manufactureꢁ to produce it in the quality
and quantities needed in today’s electronic equipment.
Electrode
Ceramic Layer
End Terminations
Terminated
Edge
Terminated
Edge
Margin
Electrodes
Formulations – Multilayer ceramic capacitors are available
in both Class ± and Class 2 formulations. Temperature
compensating formulation are Class ± and temperature
stable and general application formulations are classified
as Class 2.
Class 2 – EIA Class 2 capacitors typically are based on the
chemistry of barium titanate and provide a wide range of
capacitance values and temperature stability. The most
commonly used Class 2 dielectrics are X7R and Y1ꢀ. The
X7R provides intermediate capacitance values which vary
only ±±15 over the temperature range of -11°C to ±21°C. It
finds applications where stability over a wide temperature
range is required.
Class 1 – Class ± capacitors or temperature compensating
capacitors are usually made from mixtures of titanates
where barium titanate is normally not a major part of the
mix. They have predictable temperature coefficients and
in generalꢁ do not have an aging characteristic. Thus they
are the most stable capacitor available. The most popular
Class ± multilayer ceramic capacitors are C0G (NP0z
temperature compensating capacitors (negative-positive
0 ppm/°Cz.
The Y1ꢀ provides the highest capacitance values and is
used in applications where limited temperature changes are
expected. The capacitance value for Y1ꢀ can vary from
225 to -ꢃ25 over the -30°C to ꢃ1°C temperature range.
The Z1U dielectric is between X7R and Y1ꢀ in both stability
and capacitance range.
All Class 2 capacitors vary in capacitance value under the
influence of temperatureꢁ operating voltage (both AC and
VCzꢁ and frequency. For additional information on perfor-
mance changes with operating conditionsꢁ consult AꢀX’s
softwareꢁ SpiCap.
36
General Description
Effects of Voltage – ꢀariations in voltage have little effect
on Class ± dielectric but does affect the capacitance and
dissipation factor of Class 2 dielectrics. The application of
VC voltage reduces both the capacitance and dissipation
factor while the application of an AC voltage within a
reasonable range tends to increase both capacitance and
dissipation factor readings. If a high enough AC voltage is
appliedꢁ eventually it will reduce capacitance just as a VC
voltage will. Figure 2 shows the effects of AC voltage.
Cap. Change vs. D.C. Volts
AVX X7R T.C.
2.5
0
-2.5
-5
-7.5
-10
Cap. Change vs. A.C. Volts
AVX X7R T.C.
25%
50%
Percent Rated Volts
Figure 4
75%
100%
50
40
30
20
Typical Cap. Change vs. Temperature
AVX X7R T.C.
+20
+10
0
10
0
0VDC
RVDC
12.5
25
37.5
50
Volts AC at 1.0 KHz
Figure 2
-10
Capacitor specifications specify the AC voltage at which to
measure (normally 0.1 or ± ꢀACz and application of the
wrong voltage can cause spurious readings. Figure 3 gives
the voltage coefficient of dissipation factor for various AC
voltages at ± kilohertH. Applications of different frequencies
will affect the percentage changes versus voltages.
-20
-30
-55 -35 -15 +5 +25 +45 +65 +85 +105 +125
Temperature Degrees Centigrade
Figure 5
D.F. vs. A.C. Measurement Volts
AVX X7R T.C.
Effects of Time – Class 2 ceramic capacitors change
capacitance and dissipation factor with time as well as tem-
peratureꢁ voltage and frequency. This change with time is
known as aging. Aging is caused by a gradual re-alignment
of the crystalline structure of the ceramic and produces an
exponential loss in capacitance and decrease in dissipation
factor versus time. A typical curve of aging rate for semi-
stable ceramics is shown in Figure 6.
10.0
Curve 1 - 100 VDC Rated Capacitor
Curve 2 - 50 VDC Rated Capacitor
Curve 3 - 25 VDC Rated Capacitor
Curve 3
Curve 2
8.0
6.0
4.0
If a Class 2 ceramic capacitor that has been sitting on the
shelf for a period of timeꢁ is heated above its curie pointꢁ
Curve 1
2.0
0
±
(±21°C for 4 hours or ±10°C for ⁄
2
hour will sufficez the part
will de-age and return to its initial capacitance and dissi-
pation factor readings. Because the capacitance changes
rapidlyꢁ immediately after de-agingꢁ the basic capacitance
measurements are normally referred to a time period some-
time after the de-aging process. ꢀarious manufacturers use
different time bases but the most popular one is one day
or twenty-four hours after “last heat.” Change in the aging
curve can be caused by the application of voltage and
other stresses. The possible changes in capacitance due to
de-aging by heating the unit explain why capacitance
changes are allowed after testꢁ such as temperature cyclingꢁ
moisture resistanceꢁ etc.ꢁ in MIL specs. The application of
high voltages such as dielectric withstanding voltages also
.5
1.0
1.5
2.0
2.5
AC Measurement Volts at 1.0 KHz
Figure 3
The effect of the application of VC voltage is shown in
Figure 4. The voltage coefficient is more pronounced for
higher K dielectrics. These figures are shown for room tem-
perature conditions. The combination characteristic known
as voltage temperature limits which shows the effects of
rated voltage over the operating temperature range is
shown in Figure 1 for the military BX characteristic.
37
General Description
tends to de-age capacitors and is why re-reading of capac-
itance after ±2 or 24 hours is allowed in military specifica-
tions after dielectric strength tests have been performed.
Effects of Mechanical Stress – ꢂigh “K” dielectric
ceramic capacitors exhibit some low level pieHoelectric
reactions under mechanical stress. As a general statementꢁ
the pieHoelectric output is higherꢁ the higher the dielectric
constant of the ceramic. It is desirable to investigate this
effect before using high “K” dielectrics as coupling capaci-
tors in extremely low level applications.
Typical Curve of Aging Rate
X7R Dielectric
+1.5
0
Reliability – ꢂistorically ceramic capacitors have been one
of the most reliable types of capacitors in use today.
The approximate formula for the reliability of a ceramic
capacitor is:
-1.5
Lo
Lt
Vt
X
Tt
Y
=
͑ ͑
͑ ͑
V
T
o
o
-3.0
-4.5
where
Lo = operating life
Lt = test life
Vt = test voltage
Tt = test temperature and
To = operating temperature
in °C
Vo = operating voltage
X,Y = see text
-6.0
-7.5
ꢂistorically for ceramic capacitors exponent X has been
considered as 3. The exponent Y for temperature effects
typically tends to run about ꢃ.
1
10
100 1000 10,000 100,000
Hours
Characteristic Max. Aging Rate %/Decade
None
C0G (NP0)
X7R
Z5U
A capacitor is a component which is capable of storing
electrical energy. It consists of two conductive plates (elec-
trodesz separated by insulating material which is called the
dielectric. A typical formula for determining capacitance is:
2
3
5
Y5V
Figure 6
.224 KA
Effects of Frequency – Frequency affects capacitance
and impedance characteristics of capacitors. This effect is
much more pronounced in high dielectric constant ceramic
formulation that is low K formulations. AꢀX’s SpiCap soft-
ware generates impedanceꢁ ESRꢁ series inductanceꢁ series
resonant frequency and capacitance all as functions of fre-
quencyꢁ temperature and VC bias for standard chip siHes
and styles. It is available free from AꢀX.
C =
t
C = capacitance (picofaradsz
K = dielectric constant (ꢀacuum = ±z
A = area in square inches
t = separation between the plates in inches
(thickness of dielectricz
.224 = conversion constant
(.0ꢃꢃ4 for metric system in cmz
Capacitance – The standard unit of capacitance is the
farad. A capacitor has a capacitance of ± farad when ±
coulomb charges it to ± volt. One farad is a very large unit
-6
and most capacitors have values in the micro (±0 zꢁ nano
-9
-±2
(±0 z or pico (±0 z farad level.
Dielectric Constant – In the formula for capacitance given
above the dielectric constant of a vacuum is arbitrarily cho-
sen as the number ±. Vielectric constants of other materials
are then compared to the dielectric constant of a vacuum.
Dielectric Thickness – Capacitance is indirectly propor-
tional to the separation between electrodes. Lower voltage
requirements mean thinner dielectrics and greater capaci-
tance per volume.
Area – Capacitance is directly proportional to the area of
the electrodes. Since the other variables in the equation are
usually set by the performance desiredꢁ area is the easiest
parameter to modify to obtain a specific capacitance within
a material group.
38
General Description
Energy Stored – The energy which can be stored in a
capacitor is given by the formula:
I (Ideal)
I (Actual)
E = 1⁄ CV2
2
Loss
Angle
Phase
Angle
E = energy in joules (watts-secz
V = applied voltage
␦
C = capacitance in farads
f
Potential Change – A capacitor is a reactive component
which reacts against a change in potential across it. This is
shown by the equation for the linear charge of a capacitor:
V
IRs
dV
dt
In practice the current leads the voltage by some other
phase angle due to the series resistance RS. The comple-
ment of this angle is called the loss angle and:
Iideal
=
C
where
I = Current
C = Capacitance
dV/dt = Slope of voltage transition across capacitor
Power Factor (P.F.z = Cos f or Sine ␦
Vissipation Factor (V.F.z = tan ␦
Thus an infinite current would be required to instantly
change the potential across a capacitor. The amount of
current a capacitor can “sink” is determined by the above
equation.
for small values of ␦ the tan and sine are essentially equal
which has led to the common interchangeability of the two
terms in the industry.
Equivalent Circuit – A capacitorꢁ as a practical deviceꢁ
exhibits not only capacitance but also resistance and induc-
tance. A simplified schematic for the equivalent circuit is:
Equivalent Series Resistance – The term E.S.R. or
Equivalent Series Resistance combines all losses both
series and parallel in a capacitor at a given frequency so
that the equivalent circuit is reduced to a simple R-C series
connection.
C = Capacitance
L = Inductance
Rp = Parallel Resistance
Rs = Series Resistance
R P
E.S.R.
C
L
R S
Dissipation Factor – The VF/PF of a capacitor tells what
percent of the apparent power input will turn to heat in the
capacitor.
C
Reactance – Since the insulation resistance (Rpz is normally
very highꢁ the total impedance of a capacitor is:
E.S.R.
Dissipation Factor =
= (2 π fC) (E.S.R.)
XC
The watts loss are:
2
2
Z = RS + (XC - XLz
ͱ
Watts loss = (2 π fCV2) (D.F.)
where
Z = Total Impedance
Rs = Series Resistance
XC = Capacitive Reactance =
ꢀery low values of dissipation factor are expressed as their
reciprocal for convenience. These are called the “Q” or
Quality factor of capacitors.
±
2 π fC
Parasitic Inductance – The parasitic inductance of capac-
itors is becoming more and more important in the decou-
pling of today’s high speed digital systems. The relationship
between the inductance and the ripple voltage induced on
the VC voltage line can be seen from the simple inductance
equation:
XL = Inductive Reactance = 2 π fL
The variation of a capacitor’s impedance with frequency
determines its effectiveness in many applications.
Phase Angle – Power Factor and Vissipation Factor are
often confused since they are both measures of the loss in a
capacitor under AC application and are often almost identi-
cal in value. In a “perfect” capacitor the current in the
capacitor will lead the voltage by 90°.
di
dt
ꢀ = L
39
General Description
di
dt
is determined by dividing the rated voltage by IR (Ohm’s
Lawz.
The
seen in current microprocessors can be as high as
0.3 A/nsꢁ and up to ±0A/ns. At 0.3 A/nsꢁ ±00pꢂ of parasitic
inductance can cause a voltage spike of 30mꢀ. While this
does not sound very drasticꢁ with the ꢀcc for microproces-
sors decreasing at the current rateꢁ this can be a fairly large
percentage.
Dielectric Strength – Vielectric Strength is an expression
of the ability of a material to withstand an electrical stress.
Although dielectric strength is ordinarily expressed in voltsꢁ it
is actually dependent on the thickness of the dielectric and
thus is also more generically a function of volts/mil.
Another importantꢁ often overlookedꢁ reason for knowing
the parasitic inductance is the calculation of the resonant
frequency. This can be important for high frequencyꢁ by-
pass capacitorsꢁ as the resonant point will give the most
signal attenuation. The resonant frequency is calculated
from the simple equation:
Dielectric Absorption – A capacitor does not discharge
instantaneously upon application of a short circuitꢁ but
drains gradually after the capacitance proper has been dis-
charged. It is common practice to measure the dielectric
absorption by determining the “reappearing voltage” which
appears across a capacitor at some point in time after it has
been fully discharged under short circuit conditions.
fres =
±
ͱ
2 LC
Corona – Corona is the ioniHation of air or other vapors
which causes them to conduct current. It is especially
prevalent in high voltage units but can occur with low voltages
as well where high voltage gradients occur. The energy
discharged degrades the performance of the capacitor and
can in time cause catastrophic failures.
Insulation Resistance – Insulation Resistance is the resis-
tance measured across the terminals of a capacitor and
consists principally of the parallel resistance RP shown in
the equivalent circuit. As capacitance values and hence the
area of dielectric increasesꢁ the I.R. decreases and hence
the product (C x IR or RCz is often specified in ohm farads
or more commonly megohm-microfarads. Leakage current
40
Surface Mounting Guide
MLC Chip Capacitors
Component Pad Design
Component pads should be designed to achieve good sol-
der filets and minimiHe component movement during reflow
soldering. Pad designs are given below for the most com-
mon siHes of multilayer ceramic capacitors for both wave
and reflow soldering. The basis of these designs is:
• Pad width equal to component width. It is permissible to
decrease this to as low as ꢃ15 of component width but it
is not advisable to go below this.
• Pad overlap 0.1mm beneath component.
• Pad extension 0.1mm beyond components for reflow and
±.0mm for wave soldering.
REFLOW SOLDERING
Case Size
0402
D1
D2
D3
D4
D5
D2
±.70 (0.07z
2.30 (0.09z
3.00 (0.±2z
4.00 (0.±6z
4.00 (0.±6z
1.60 (0.22z
1.60 (0.22z
1.60 (0.22z
6.60 (0.26z
6.60 (0.26z
0.60 (0.02z
0.ꢃ0 (0.03z
±.00 (0.04z
±.00 (0.04z
±.00 (0.04z
±.00 (0.04z
±.00 (0.04zz
±.00 (0.04z
±.00 (0.04z
±.00 (0.04z
0.10 (0.02z
0.70 (0.03z
±.00 (0.04z
2.00 (0.09z
2.00 (0.09z
3.60 (0.±4z
3.60 (0.±4z
3.60 (0.±4z
4.60 (0.±ꢃz
4.60 (0.±ꢃz
0.60 (0.02z
0.ꢃ0 (0.03z
±.00 (0.04z
±.00 (0.04z
±.00 (0.04z
±.00 (0.04z
±.00 (0.04z
±.00 (0.04z
±.00 (0.04z
±.00 (0.04z
0.10 (0.02z
0.71 (0.03z
±.21 (0.01z
±.60 (0.06z
2.10 (0.±0z
2.00 (0.0ꢃz
3.00 (0.±2z
6.31 (0.21z
1.00 (0.20z
6.31 (0.21z
0603
0805
1206
1210
1808
1812
1825
2220
D1
D3
D4
D5
2225
Dimensions in millimeters (inches)
41
Surface Mounting Guide
MLC Chip Capacitors
WAVE SOLDERING
D2
Case Size
0603
D1
D2
D3
D4
D5
3.±0 (0.±2z
4.00 (0.±1z
1.00 (0.±9z
1.00 (0.±9z
±.20 (0.01z
±.10 (0.06z
±.10 (0.06z
±.10 (0.06z
0.70 (0.03z
±.00 (0.04z
2.00 (0.09z
2.00 (0.09z
±.20 (0.01z
±.10 (0.06z
±.10 (0.06z
±.10 (0.06z
0.71 (0.03z
±.21 (0.01z
±.60 (0.06z
2.10 (0.±0z
D1
D3
D4
0805
1206
1210
D5
Dimensions in millimeters (inches)
Component Spacing
Preheat & Soldering
For wave soldering componentsꢁ must be spaced sufficiently
far apart to avoid bridging or shadowing (inability of solder
to penetrate properly into small spacesz. This is less impor-
tant for reflow soldering but sufficient space must be
allowed to enable rework should it be required.
The rate of preheat should not exceed 4°C/second to
prevent thermal shock. A better maximum figure is about
2°C/second.
For capacitors siHe ±206 and belowꢁ with a maximum
thickness of ±.21mmꢁ it is generally permissible to allow a
temperature differential from preheat to soldering of ±10°C.
In all other cases this differential should not exceed ±00°C.
For further specific application or process adviceꢁ please
consult AꢀX.
≥1.5mm (0.06)
≥1mm (0.04)
Cleaning
Care should be taken to ensure that the capacitors are
thoroughly cleaned of flux residues especially the space
beneath the capacitor. Such residues may otherwise
become conductive and effectively offer a low resistance
bypass to the capacitor.
≥1mm (0.04)
Ultrasonic cleaning is permissibleꢁ the recommended
conditions being ꢃ Watts/litre at 20-41 kꢂHꢁ with a process
cycle of 2 minutes vapor rinseꢁ 2 minutes immersion in the
ultrasonic solvent bath and finally 2 minutes vapor rinse.
42
Surface Mounting Guide
MLC Chip Capacitors
General
APPLICATION NOTES
Surface mounting chip multilayer ceramic capacitors
are designed for soldering to printed circuit boards or other
substrates. The construction of the components is such that
they will withstand the time/temperature profiles used in both
wave and reflow soldering methods.
Storage
Good solderability is maintained for at least twelve monthsꢁ
provided the components are stored in their “as received”
packaging at less than 40°C and 705 Rꢂ.
Solderability
Handling
Terminations to be well soldered after immersion in a 60/40
tin/lead solder bath at 231 ±1°C for 2±± seconds.
Chip multilayer ceramic capacitors should be handled with
care to avoid damage or contamination from perspiration
and skin oils. The use of tweeHers or vacuum pick ups
is strongly recommended for individual components. Bulk
handling should ensure that abrasion and mechanical shock
are minimiHed. Taped and reeled components provides the
ideal medium for direct presentation to the placement
machine. Any mechanical shock should be minimiHed during
handling chip multilayer ceramic capacitors.
Leaching
Terminations will resist leaching for at least the immersion
times and conditions shown below.
Solder
Tin/Lead/Silver Temp. °C
60/40/0 260±1
Solder
Immersion Time
Seconds
Termination Type
Nickel Barrier
30±±
Preheat
It is important to avoid the possibility of thermal shock during
soldering and carefully controlled preheat is therefore
required. The rate of preheat should not exceed 4°C/second
and a target figure 2°C/second is recommended. Although
an ꢃ0°C to ±20°C temperature differential is preferredꢁ
recent developments allow a temperature differential
between the component surface and the soldering temper-
ature of ±10°C (Maximumz for capacitors of ±2±0 siHe and
below with a maximum thickness of ±.21mm. The user is
cautioned that the risk of thermal shock increases as chip
siHe or temperature differential increases.
Recommended Soldering Profiles
Reflow
300
Natural
Cooling
Preheat
210
200
220°C
±10
±00
10
to
210°C
Soldering
Mildly activated rosin fluxes are preferred. The minimum
amount of solder to give a good joint should be used.
Excessive solder can lead to damage from the stresses
caused by the difference in coefficients of expansion
between solderꢁ chip and substrate. AꢀX terminations are
suitable for all wave and reflow soldering systems. If hand
soldering cannot be avoidedꢁ the preferred technique is the
utiliHation of hot air soldering tools.
0
±min
(MinimiHe soldering timez
±0 sec. max
±min
Wave
Cooling
Natural cooling in air is preferredꢁ as this minimiHes stresses
within the soldered joint. When forced air cooling is usedꢁ
cooling rate should not exceed 4°C/second. Quenching
is not recommended but if usedꢁ maximum temperature
differentials should be observed according to the preheat
conditions above.
300
Preheat
Natural
Cooling
210
200
±10
±00
10
T
230°C
to
Cleaning
210°C
Flux residues may be hygroscopic or acidic and must be
removed. AꢀX MLC capacitors are acceptable for use with
all of the solvents described in the specifications MIL-STV-
202 and EIA-RS-±9ꢃ. Alcohol based solvents are acceptable
and properly controlled water cleaning systems are also
acceptable. Many other solvents have been proven successfulꢁ
and most solvents that are acceptable to other components
on circuit assemblies are equally acceptable for use with
ceramic capacitors.
0
± to 2 min
3 sec. max
(Preheat chips before solderingz
T/maximum ±10°C
43
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